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<a name="ARC-Directives"></a>
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Next: <a href="ARC-Modifiers.html#ARC-Modifiers" accesskey="n" rel="next">ARC Modifiers</a>, Previous: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="p" rel="prev">ARC Syntax</a>, Up: <a href="ARC_002dDependent.html#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="ARC-Machine-Directives"></a>
<h4 class="subsection">9.3.3 ARC Machine Directives</h4>

<a name="index-machine-directives_002c-ARC"></a>
<a name="index-ARC-machine-directives"></a>
<p>The ARC version of <code>as</code> supports the following additional
machine directives:
</p>
<dl compact="compact">
<dd>
<a name="index-lcomm-directive-1"></a>
</dd>
<dt><code>.lcomm <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></dt>
<dd><p>Reserve <var>length</var> (an absolute expression) bytes for a local common
denoted by <var>symbol</var>.  The section and value of <var>symbol</var> are
those of the new local common.  The addresses are allocated in the bss
section, so that at run-time the bytes start off zeroed.  Since
<var>symbol</var> is not declared global, it is normally not visible to
<code>ld</code>.  The optional third parameter, <var>alignment</var>,
specifies the desired alignment of the symbol in the bss section,
specified as a byte boundary (for example, an alignment of 16 means
that the least significant 4 bits of the address should be zero).  The
alignment must be an absolute expression, and it must be a power of
two.  If no alignment is specified, as will set the alignment to the
largest power of two less than or equal to the size of the symbol, up
to a maximum of 16.
</p>
<a name="index-lcommon-directive_002c-ARC"></a>
</dd>
<dt><code>.lcommon <var>symbol</var>, <var>length</var>[, <var>alignment</var>]</code></dt>
<dd><p>The same as <code>lcomm</code> directive.
</p>
<a name="index-cpu-directive_002c-ARC"></a>
</dd>
<dt><code>.cpu <var>cpu</var></code></dt>
<dd><p>The <code>.cpu</code> directive must be followed by the desired core
version.  Permitted values for CPU are:
</p><dl compact="compact">
<dt><code>ARC600</code></dt>
<dd><p>Assemble for the ARC600 instruction set.
</p>
</dd>
<dt><code>ARC700</code></dt>
<dd><p>Assemble for the ARC700 instruction set.
</p>
</dd>
<dt><code>NPS400</code></dt>
<dd><p>Assemble for the NPS400 instruction set.
</p>
</dd>
<dt><code>EM</code></dt>
<dd><p>Assemble for the ARC EM instruction set.
</p>
</dd>
<dt><code>HS</code></dt>
<dd><p>Assemble for the ARC HS instruction set.
</p>
</dd>
</dl>

<p>Note: the <code>.cpu</code> directive overrides the command line option
<code>-mcpu=<var>cpu</var></code>; a warning is emitted when the version is not
consistent between the two.
</p>
</dd>
<dt><code>.extAuxRegister <var>name</var>, <var>addr</var>, <var>mode</var></code></dt>
<dd><a name="index-extAuxRegister-directive_002c-ARC"></a>
<p>Auxiliary registers can be defined in the assembler source code by
using this directive.  The first parameter, <var>name</var>, is the name of the
new auxiliary register.  The second parameter, <var>addr</var>, is
address the of the auxiliary register.  The third parameter,
<var>mode</var>, specifies whether the register is readable and/or writable
and is one of:
</p><dl compact="compact">
<dt><code>r</code></dt>
<dd><p>Read only;
</p>
</dd>
<dt><code>w</code></dt>
<dd><p>Write only;
</p>
</dd>
<dt><code>r|w</code></dt>
<dd><p>Read and write.
</p>
</dd>
</dl>

<p>For example:
</p><div class="example">
<pre class="example">	.extAuxRegister mulhi, 0x12, w
</pre></div>
<p>specifies a write only extension auxiliary register, <var>mulhi</var> at
address 0x12.
</p>
</dd>
<dt><code>.extCondCode <var>suffix</var>, <var>val</var></code></dt>
<dd><a name="index-extCondCode-directive_002c-ARC"></a>
<p>ARC supports extensible condition codes.  This directive defines a new
condition code, to be known by the suffix, <var>suffix</var> and will
depend on the value, <var>val</var> in the condition code.
</p>
<p>For example:
</p><div class="example">
<pre class="example">	.extCondCode is_busy,0x14
	add.is_busy  r1,r2,r3
</pre></div>
<p>will only execute the <code>add</code> instruction if the condition code
value is 0x14.
</p>
</dd>
<dt><code>.extCoreRegister <var>name</var>, <var>regnum</var>, <var>mode</var>, <var>shortcut</var></code></dt>
<dd><a name="index-extCoreRegister-directive_002c-ARC"></a>
<p>Specifies an extension core register named <var>name</var> as a synonym for
the register numbered <var>regnum</var>.  The register number must be
between 32 and 59.  The third argument, <var>mode</var>, indicates whether
the register is readable and/or writable and is one of:
</p><dl compact="compact">
<dt><code>r</code></dt>
<dd><p>Read only;
</p>
</dd>
<dt><code>w</code></dt>
<dd><p>Write only;
</p>
</dd>
<dt><code>r|w</code></dt>
<dd><p>Read and write.
</p>
</dd>
</dl>

<p>The final parameter, <var>shortcut</var> indicates whether the register has
a short cut in the pipeline.  The valid values are:
</p><dl compact="compact">
<dt><code>can_shortcut</code></dt>
<dd><p>The register has a short cut in the pipeline;
</p>
</dd>
<dt><code>cannot_shortcut</code></dt>
<dd><p>The register does not have a short cut in the pipeline.
</p></dd>
</dl>

<p>For example:
</p><div class="example">
<pre class="example">	.extCoreRegister mlo, 57, r , can_shortcut
</pre></div>
<p>defines a read only extension core register, <code>mlo</code>, which is
register 57, and can short cut the pipeline.
</p>
</dd>
<dt><code>.extInstruction <var>name</var>, <var>opcode</var>, <var>subopcode</var>, <var>suffixclass</var>, <var>syntaxclass</var></code></dt>
<dd><a name="index-extInstruction-directive_002c-ARC"></a>
<p>ARC allows the user to specify extension instructions.  These
extension instructions are not macros; the assembler creates encodings
for use of these instructions according to the specification by the
user.
</p>
<p>The first argument, <var>name</var>, gives the name of the instruction.
</p>
<p>The second argument, <var>opcode</var>, is the opcode to be used (bits 31:27
in the encoding).
</p>
<p>The third argument, <var>subopcode</var>, is the sub-opcode to be used, but
the correct value also depends on the fifth argument,
<var>syntaxclass</var>
</p>
<p>The fourth argument, <var>suffixclass</var>, determines the kinds of
suffixes to be allowed.  Valid values are:
</p><dl compact="compact">
<dt><code>SUFFIX_NONE</code></dt>
<dd><p>No suffixes are permitted;
</p>
</dd>
<dt><code>SUFFIX_COND</code></dt>
<dd><p>Conditional suffixes are permitted;
</p>
</dd>
<dt><code>SUFFIX_FLAG</code></dt>
<dd><p>Flag setting suffixes are permitted.
</p>
</dd>
<dt><code>SUFFIX_COND|SUFFIX_FLAG</code></dt>
<dd><p>Both conditional and flag setting suffices are permitted.
</p>
</dd>
</dl>

<p>The fifth and final argument, <var>syntaxclass</var>, determines the syntax
class for the instruction.  It can have the following values:
</p><dl compact="compact">
<dt><code>SYNTAX_2OP</code></dt>
<dd><p>Two Operand Instruction;
</p>
</dd>
<dt><code>SYNTAX_3OP</code></dt>
<dd><p>Three Operand Instruction.
</p>
</dd>
<dt><code>SYNTAX_1OP</code></dt>
<dd><p>One Operand Instruction.
</p>
</dd>
<dt><code>SYNTAX_NOP</code></dt>
<dd><p>No Operand Instruction.
</p></dd>
</dl>

<p>The syntax class may be followed by &lsquo;<samp>|</samp>&rsquo; and one of the following
modifiers.
</p><dl compact="compact">
<dt><code>OP1_MUST_BE_IMM</code></dt>
<dd><p>Modifies syntax class <code>SYNTAX_3OP</code>, specifying that the first
operand of a three-operand instruction must be an immediate (i.e., the
result is discarded).  This is usually used to set the flags using
specific instructions and not retain results.
</p>
</dd>
<dt><code>OP1_IMM_IMPLIED</code></dt>
<dd><p>Modifies syntax class <code>SYNTAX_20P</code>, specifying that there is an
implied immediate destination operand which does not appear in the
syntax.
</p>
<p>For example, if the source code contains an instruction like:
</p><div class="example">
<pre class="example">inst r1,r2
</pre></div>
<p>the first argument is an implied immediate (that is, the result is
discarded).  This is the same as though the source code were: inst
0,r1,r2.
</p>
</dd>
</dl>

<p>For example, defining a 64-bit multiplier with immediate operands:
</p><div class="example">
<pre class="example">	.extInstruction  mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
			 SYNTAX_3OP|OP1_MUST_BE_IMM
</pre></div>
<p>which specifies an extension instruction named <code>mp64</code> with 3
operands.  It sets the flags and can be used with a condition code,
for which the first operand is an immediate, i.e. equivalent to
discarding the result of the operation.
</p>
<p>A two operands instruction variant would be:
</p><div class="example">
<pre class="example">	.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
	SYNTAX_2OP|OP1_IMM_IMPLIED
</pre></div>
<p>which describes a two operand instruction with an implicit first
immediate operand.  The result of this operation would be discarded.
</p>
</dd>
</dl>

<hr>
<div class="header">
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Next: <a href="ARC-Modifiers.html#ARC-Modifiers" accesskey="n" rel="next">ARC Modifiers</a>, Previous: <a href="ARC-Syntax.html#ARC-Syntax" accesskey="p" rel="prev">ARC Syntax</a>, Up: <a href="ARC_002dDependent.html#ARC_002dDependent" accesskey="u" rel="up">ARC-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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